Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same

ABSTRACT

An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

PRIORITY STATEMENT

The present application is a divisional of U.S. application Ser. No.12/010,807, filed Jan. 30, 2008, which claims the benefit of priorityunder 35 U.S.C. §119 from Korean Patent Application No. 10-2007-0016525,filed on Feb. 16, 2007, the disclosure of which is hereby incorporatedherein by reference in its entirety.

BACKGROUND

1. Technical Field

Example embodiments relate to a bonding pad structure and a method offabricating the same. Other example embodiments relate to an electronicdevice having a bonding pad structure and a method of fabricating thesame.

2. Discussion of the Related Art

In recent years, electronic products and communication devices have beenscaled-down and/or manufactured to operate with a higher performance.Due to this trend, researchers are looking for various ways to develophigher-performing electronic devices (e.g., a semiconductor chipincluding the electronic products and the communication devices) and/ordecrease the size of the electronic products and the communicationdevices. In order to decrease the size of the electronic devices (e.g.,the semiconductor chip), semiconductor manufacturing techniques havebeen developed with regard to fine line widths, multi-layered metalinterconnection lines and the like.

Semiconductor manufacturing techniques, which use multi-layered metalinterconnection lines, have been widely researched and used. Themulti-layered metal interconnection lines may be formed of copper (Cu)interconnects having a damascene interconnect structure with lowresistivity and/or high reliability in order to increase the performanceof the semiconductor chip.

There are limits to decreasing the size of the electronic device usingthe conventional semiconductor manufacturing techniques for forming fineline widths and the multi-layered metal interconnection lines. In orderto decrease the size of the electronic device, the bonding pad pitch maybe reduced. The bonding pad may contact a bonding wire that electricallyconnects the semiconductor chip and a printed circuit board.

A bonding pad structure of the semiconductor device using Cuinterconnects has been acknowledged in the art. A bonding pad structureformed of an aluminum layer may be formed on a substrate having the Cuinterconnects. According to the conventional art, the Cu interconnectsmay be used to increase the performance of the electronic device. Aplurality of bonding pad structures may be formed at a same level.Because there are limits to reducing the distance between the bondingpads positioned at a same level, there are also limits to reducing thebonding pad pitch. As such, it may be difficult to decrease thetwo-dimensional area occupied by the bonding pads in the semiconductorchip.

SUMMARY

Example embodiments relate to a bonding pad structure and a method offabricating the same. Other example embodiments relate to an electronicdevice having a bonding pad structure and a method of fabricating thesame.

Example embodiments are directed a bonding pad structure which iscapable of decreasing (or reducing) a bonding pad pitch.

In accordance with example embodiments, a bonding pad structure mayinclude a first bonding pad formed on a substrate. A second bonding pad,which is spaced apart from the first bonding pad, may be formed having atop surface positioned at a higher level than the first bonding pad.

The second bonding pad may have a first region positioned at the samelevel as the first bonding pad and a second region positioned (orformed) at a higher level than the first bonding pad. The second regionmay have a greater width than that of the first region. The firstbonding pad and the second bonding pad may have bottom surfaces whichare positioned at a same level.

The bonding pad structure may include an insulating layer, which isinterposed between the first bonding pad and the second bonding pad. Theinsulating layer may have a top surface, which is positioned (or formed)at a higher level than the first bonding pad. The second bonding pad maybe formed on (or over) a portion of a top surface of the insulatinglayer.

The bonding pad structure may include an insulating spacer provided on aside wall of the second bonding pad. The insulating spacer may be formedon (or covering) the side wall of the second bonding pad and a portionof the first bonding pad.

In example embodiments, an electronic device having a bonding padstructure is provided. The electronic device includes a lower insulatinglayer provided on a substrate. First bonding pads, which pass through(or are formed between) the lower insulating layer, are provided. Anupper insulating layer may be provided on the lower insulating layeraround the first bonding pads. Second bonding pads may sequentially passthrough (or be formed between) the upper insulating layer and the lowerinsulating layer, respectively. The second bonding pads may be spacedapart from the first bonding pads. The second bonding pads may have atop surface positioned at a higher level than the first bonding pads.

The electronic device may include an interlayer insulating layer and/ormetal patterns. The interlayer insulating layer may be interposedbetween the substrate and the lower insulating layer. The metal patternsmay pass through (or be formed between) the interlayer insulating layer.The metal patterns may be electrically connected to the first bondingpads and the second bonding pads. Each of the first bonding pads may beformed on (or covering) a portion of a top surface of the lowerinsulating layer.

The upper insulating layer may be formed on (or covering) a portion oftop surfaces of the first bonding pads. The second bonding pads may beformed on (or covering) a portion of a top surface of the upperinsulating layer.

The electronic device may include insulating spacers on side walls ofthe second bonding pads. The insulating spacer may be formed on (orcovering) the side walls of the second bonding pads and a portion of thefirst bonding pads.

According to example embodiments, a method of fabricating a bonding padstructure includes forming a first bonding pad on a substrate, forming asecond bonding pad spaced apart from the first bonding pad, wherein atop surface of the second bonding pad is formed at a higher level thanthe first bonding pad.

According to other example embodiments, a method of fabricating anelectronic device having a bonding pad structure is provided. The methodincludes forming a lower insulating layer on the substrate. Firstbonding pads may be formed passing through (or between) the lowerinsulating layer. An upper insulating layer may be formed on thesubstrate having the first bonding pads. Second bonding pads may beformed sequentially passing through (or between) the upper insulatinglayer and the lower insulating layer, respectively. The second bondingpads may be spaced apart from the first bonding pads. The second bondingpads may have a top surface positioned at a higher level than the firstbonding pads. The upper insulating layer may be etched using the secondbonding pads as etching masks so as to expose top surfaces of the firstbonding pads.

The method may include forming an interlayer insulating layer on thesubstrate and forming metal patterns in the interlayer insulating layer,before forming the lower insulating layer. The metal patterns may beelectrically connected to the first bonding pads and the second bondingpads.

The first bonding pads may be formed on (or covering) a portion of a topsurface of the lower insulating layer. The second bonding pads may beformed on (or covering) a portion of a top surface of the upperinsulating layer. The forming of the first bonding pads may includepattering the lower insulating layer to form first pad holes, which passthrough the lower insulating layer; forming a first pad layer on thesubstrate having the first pad holes and patterning the first pad layer.

The method may include forming the first pad layer, forming a firstbuffer layer on the first pad and patterning the first buffer layer toform first buffer patterns on the first bonding pads. Forming andpatterning the first buffer layer may be performed while patterning thefirst pad layer. The upper insulating layer may be etched using thesecond bonding pads as an etching mask. The first buffer patterns may beremoved.

The forming of the second bonding pads may include patterning the upperinsulating layer and the lower insulating layer to form second padholes, which pass through the upper insulating layer and the lowerinsulating layer, respectively, forming a second pad layer on thesubstrate having the second pad holes and patterning the second padlayer.

The method may include forming the second pad layer, forming a secondbuffer layer on the second pad layer and patterning the second bufferlayer to form second buffer patterns on the second bonding pads. Formingand patterning the second buffer layer may be performed while patterningthe second pad layer. The upper insulating layer may be etched. Thesecond buffer patterns may be removed.

The method may include forming a spacer insulating layer on thesubstrate having the second bonding pads. Top surfaces of the firstbonding pads may be exposed. The spacer insulating layer may beanisotropically etched to form insulating spacers on side walls of thesecond bonding pads. The insulating spacers may be formed on (orcovering) the side wall of the second bonding pads and a portion of thefirst bonding pads.

The method may include forming insulating spacers on the side walls ofthe second bonding pads, after forming the second bonding pads.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. FIGS. 1A-1E and 2 represent non-limiting, example embodimentsas described herein.

FIG. 1A through FIG. 1E are diagrams illustrating cross-sectional viewsof a method of fabricating an electronic device according to exampleembodiments; and

FIG. 2 is a diagram illustrating a cross-sectional view an electronicdevice according to example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully withreference to the accompanying drawings in which some example embodimentsare shown. In the drawings, the thicknesses of layers and regions may beexaggerated for clarity.

Detailed illustrative embodiments are disclosed herein. However,specific structural and functional details disclosed herein are merelyrepresentative for purposes of describing example embodiments. Thisinvention may, however, may be embodied in many alternate forms andshould not be construed as limited to only example embodiments set forthherein.

Accordingly, while example embodiments are capable of variousmodifications and alternative forms, embodiments thereof are shown byway of example in the drawings and will herein be described in detail.It should be understood, however, that there is no intent to limitexample embodiments to the particular forms disclosed, but on thecontrary, example embodiments are to cover all modifications,equivalents, and alternatives falling within the scope of the invention.Like numbers refer to like elements throughout the description of thefigures.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the scope of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or a relationship between a feature and anotherelement or feature as illustrated in the figures. It will be understoodthat the spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the Figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, for example, the term “below” can encompass both anorientation which is above as well as below. The device may be otherwiseoriented (rotated 90 degrees or viewed or referenced at otherorientations) and the spatially relative descriptors used herein shouldbe interpreted accordingly.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures). As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, may be expected. Thus,example embodiments should not be construed as limited to the particularshapes of regions illustrated herein but may include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient (e.g., of implant concentration) at its edgesrather than an abrupt change from an implanted region to a non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation may take place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes donot necessarily illustrate the actual shape of a region of a device anddo not limit the scope.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

In order to more specifically describe example embodiments, variousaspects will be described in detail with reference to the attacheddrawings. However, the present invention is not limited to exampleembodiments described.

Example embodiments relate to a bonding pad structure and a method offabricating the same. Other example embodiments relate to an electronicdevice having a bonding pad structure and a method of fabricating thesame.

FIG. 1A through FIG. 1E are diagrams illustrating cross-sectional viewsof a method of fabricating an electronic device according to exampleembodiments. FIG. 2 is a diagram illustrating a cross-sectional viewillustrating an electronic device according example embodiments.

A structure of the electronic device according to example embodimentswill be described with reference to FIG. 1.

Referring to FIG. 1E, a substrate 100 is provided. The substrate 100 maybe a semiconductor substrate having a conductive region. An interlayerinsulating layer 105 may be formed on the substrate 100. The interlayerinsulating layer 105 may include a silicon oxide layer. The interlayerinsulating layer 105 may be formed of a low-k dielectric layer having alower dielectric constant than that of the silicon oxide layer in orderto increase the operating speed of a semiconductor device. For example,the low-k dielectric layer may include a fluorine-doped silicate glasslayer (FSG), a hydrogen silsesquioxane layer (HSQ), a methylsilsesquioxane layer (MSQ or SiOC) or the like.

First and second metal patterns 110 a and 110 b may be formed passingthrough (or between) the interlayer insulating layer 105. The first andsecond metal patterns 110 a and 110 b may be in contact with a desiredregion of the substrate 100. The first and second metal patterns 110 aand 110 b may be a damascene interconnect structure. For example, thefirst and second metal patterns 110 a and 110 b may be copper (Cu)interconnects having the damascene interconnect structure.

The first metal patterns 110 a and the second metal patterns 110 b maybe repeatedly arranged. One interconnection selected from among thesecond metal patterns 110 b may be positioned between two first metalpatterns 110 a selected from among the first metal patterns 110 a.

Interconnection barrier patterns 109 may be interposed between the firstand second metal patterns 110 a and 110 b and the interlayer insulatinglayer 105. The interconnection barrier patterns 109 may include a metalnitride layer (e.g., a titanium nitride layer, a tantalum nitride layeror the like). If the first and second metal patterns 110 a and 110 b mayinclude a copper layer, the interconnection barrier patterns 109 mayprevent (or reduce the likelihood of) Cu elements in the first andsecond metal patterns 110 a and 110 b from diffusing into the substrate100.

An insulating barrier layer 115 and a lower insulating layer 120 may besequentially stacked on the substrate having the first and second metalpatterns 110 a and 110 b. The insulating barrier layer 115 may be formedof a silicon nitride layer. The lower insulating layer 120 may include afirst insulating layer 117 and a second insulating layer 118,sequentially stacked. The first insulating layer 117 may include asilicon oxide layer. The second insulating layer 118 may include asilicon oxide layer or a silicon nitride layer.

Referring to FIG. 1B, first bonding pads 125 may be formed sequentiallypassing through the lower insulating layer 120 and the insulatingbarrier layer 115 such that the first bonding pads 125 are electricallyconnected to the first metal patterns 110 a. The first bonding pads 125may have a higher top surface than the lower insulating layer 120. Thefirst bonding pads 125 may be formed on (or covering) a portion of a topsurface of the lower insulating layer 120. The first bonding pads 125may be formed of an aluminum layer or an aluminum alloy layer. Thealuminum alloy layer may include an aluminum (Al) element and/or acopper (Cu) element.

First barrier patterns 123 may be formed self-aligned with the firstbonding pads 125. The first barrier patterns may be formed (or disposed)under the first bonding pads 125. The first barrier patterns 123 mayinclude a metal nitride layer (e.g., a titanium nitride layer or atantalum nitride layer).

Referring to FIG. 1C, an upper insulating layer 130 may be provided (orformed) on the lower insulating layer 120 around the first bonding pads125. The upper insulating layer 130 may include a silicon oxide layer ora silicon nitride layer.

Second bonding pads 135 may be formed sequentially passing through theupper insulating layer 130, the lower insulating layer 120 and theinsulating barrier layer 115. The second boding pads 135 may beelectrically connected to the second metal patterns 110 b. The secondbonding pads 135 may have bottom surfaces which are positioned at thesame level as the bottom surfaces of the first bonding pads 125. Each ofthe second bonding pads 135 may be positioned between the first bondingpads 125. Between the second bonding pads 135 and the first bonding pads125 may be interposed the lower insulating layer 120 and the upperinsulating layer 130. The second bonding pads 125 may be formed of thesame material as that of the first bonding pads 125.

The second bonding pads 135 have a top surface which is positioned at ahigher level than the first bonding pads 125. The second bonding pads135 may be formed on (or covering) the portion of the top surface of theupper insulating layer 130. Each of the second bonding pads 135 may havea first region which is positioned at the same level as the firstbonding pads 125 and a second region which is positioned at a higherlevel than the first bonding pads 125. The second region may have agreater width than the first region. The second region of the secondbonding pads 135 may be positioned at a higher level than the firstbonding pads 125. The second region of the second bonding pads 135 maybe formed on (or covering) a portion of the top surface of the upperinsulating layer 130.

From a plan view, the reduced distance between the second bonding pads135 and the first bonding pads 125 may be seen. For example, as shown inFIG. 1E, the side wall of the first bonding pads 125 and the side wallof the second bonding pads 135 may be positioned (or formed) in asubstantially vertical line. Although the side wall of the first bondingpads 125 and the side wall of the second bonding pads 135 are positionedin a substantially vertical line, an electric short between the firstbonding pads 125 and the second bonding pads 135 may not occur becausethe upper insulating layer 130 is interposed between the first bondingpads 125 and the second bonding pads 135.

It can be seen from a top view that a two-dimensional area, which isoccupied by the bonding pads may decrease because the distance betweenthe first bonding pads 125 and the second bonding pads 135 may bereduced (or decreased) in an electronic device (e.g., a semiconductorchip). As such, the size of the electronic device may be reduced.

Referring to FIG. 1E, second barrier patterns 133 may be formedself-aligned to the second bonding pads 135. The second barrier patterns133 may be positioned under the second bonding pads 135. The secondbarrier patterns 133 may include a metal nitride layer (e.g., a titaniumnitride layer or a tantalum nitride layer).

Insulating spacers 145 may be provided on side walls of the secondbonding pads 135. Insulating spacers 245 may be formed on (or covering)the side walls of the second bonding pads 135. The insulating spacers245 may extend downward such that the insulating spacers 245 are formedon (or covering) a portion of the first bonding pads 125. The insulatingspacers 145 and 245 may prevent (or reduce) an electric short betweenthe first bonding pads 135 and the second bonding pads 125. Theinsulating spacers 145 and 245 may include a silicon oxide layer or asilicon nitride layer.

A method of fabricating an electronic device according to exampleembodiments will be described below with reference to FIG. 1A throughFIG. 1E.

Referring to FIG. 1A, a substrate 100 is prepared. The substrate 100 mayby a semiconductor substrate including a conductive region. Thesubstrate 100 may include one or more lower metal interconnectionlayers. An interlayer insulating layer 105 may be formed on thesubstrate 100. The interlayer insulating layer 105 may be formed of asilicon oxide layer. The interlayer insulating layer 105 may include alow-k dielectric layer having a lower dielectric constant than that ofthe silicon oxide layer in order to increase the operating speed of thesemiconductor device. The low-k dielectric layer may be formed of afluorine-doped silicate glass layer (FSG), a hydrogen silsesquioxanelayer (HSQ), a methyl silsesquioxane layer (MSQ or SiOC) or the like.

Via holes and/or trenches (not shown) may be formed by patterning theinterlayer insulating layer 105. Interconnection barrier patterns 109may be formed on the inner walls of the via holes and/or the trenches.First and second metal patterns 110 a and 110 b, which fill the viaholes and/or the trenches, may be formed on the interconnection barrierpatterns 109. The first and second metal patterns 110 a and 110 b may beelectrically connected to a desired region of the substrate 100. Thefirst and second metal patterns 110 a and 110 b may be copper (Cu)interconnects. The interconnection barrier patterns 109 may include ametal nitride layer (e.g., a tantalum nitride layer or a titaniumnitride layer). The interconnection barrier patterns 109 may prevent (orreduce the likelihood of) metal elements (e.g., Cu elements) in thefirst and second metal patterns 110 a and 110 b from diffusing into thesubstrate 100. The first metal patterns 110 a and the second metalpatterns 110 b may be repeatedly arranged. One second metalinterconnection 110 b may be formed (or positioned) between two firstmetal patterns 110 a selected from among the first metal patterns 110 a.

An insulating barrier layer 115 and a lower insulating layer 120 may besequentially formed on the substrate having the first and second metalpatterns 110 a and 110 b. The insulating barrier layer 115 may be formedsuch that the insulating barrier layer 115 includes a silicon nitridelayer. The lower insulating layer 120 may be formed of a firstinsulating layer 117 and a second insulating layer 118, sequentiallystacked. The first insulating layer 117 may be formed including asilicon oxide layer or a silicon nitride layer. The second insulatinglayer 118 may be formed including a silicon oxide layer or a siliconnitride layer.

First pad holes 120 a exposing the first metal patterns 110 a may beformed by sequentially patterning the lower insulating layer 120 and theinsulating barrier layer 115. As such, the sequentially stackedinsulating barrier layer 115 and lower insulating layer 120 may beformed on (or covering) the second metal patterns 110 b, which may beformed on (or positioned) between the first pad holes 120 a.

Referring to FIG. 1B, a first barrier layer, a first pad layer and afirst buffer layer may be sequentially formed on the substrate havingthe first pad holes 120 a. The first barrier layer may include a metalnitride layer (e.g., a tantalum nitride layer or a titanium nitridelayer). The first pad layer may be formed of an aluminum layer or analuminum alloy layer. The aluminum alloy layer may include an Al elementand/or a Cu element. The first buffer layer may be formed of a materialwhich is different from that of the first pad layer. For example, thefirst buffer layer may be formed of a metal nitride layer.

First barrier patterns 123, first bonding pads 125 and first bufferpatterns 127 may be sequentially formed on the first metal patterns 110a by patterning the first barrier layer, the first pad layer and thefirst buffer layer, sequentially stacked. The first buffer patterns 127may prevent (or reduce) damage to the surface of the first bonding pads125 during subsequent processes. The first buffer patterns 127 mayprevent (or reduce) oxidation of the surface of the first bonding pads125.

The first barrier patterns 123, the first bonding pads 125 and the firstbuffer patterns 127, which are sequentially stacked, may fill the firstpad holes 120 a. The first barrier patterns 123, the first bonding pads125 and the first buffer patterns 127, which are sequentially stacked,may be formed partially covering a top surface of the lower insulatinglayer 120 around the first pad holes 120 a. As such, the first barrierpatterns 123, the first bonding pads 125 and the first buffer patterns127, which are sequentially stacked, may be formed passing through thelower insulating layer 120 and the insulating barrier layer 115. Thefirst barrier patterns 123, the first bonding pads 125 and the firstbuffer patterns 127 may be electrically connected to the first metalpatterns 110 a. The first barrier patterns 123, the first bonding pads125 and the first buffer patterns 127 may have a top surface which ispositioned at a higher level than the lower insulating layer 120. thefirst bonding pads 125 may have a region which is positioned at a higherlevel than the lower insulating layer 120.

Referring to FIG. 1C, an upper insulating layer 130 may be formed on thesubstrate having the first barrier patterns 123, the first bonding pads125 and the first buffer patterns 127, sequentially stacked. The upperinsulating layer may include a silicon oxide layer or a silicon nitridelayer. Second pad holes 130 a may be formed by patterning the upperinsulating layer 130, the lower insulating layer 120 and the insulatingbarrier layer 115 to expose the second metal patterns 110 b.

Referring to FIG. 1D, a second barrier layer, a second pad layer and asecond buffer layer, which are sequentially stacked, may be formed onthe substrate having the second pad holes 130 a. The second barrierlayer may include a metal nitride layer (e.g., a titanium nitride layeror a tantalum nitride layer). The second pad layer may be formed of analuminum layer or an aluminum alloy layer. The aluminum alloy layer mayinclude Al element and Cu element. The second buffer layer may be formedof the same material as that of the first buffer patterns 127. Maskpatterns 140 may be formed on the second buffer layer. The mask patterns140 may be formed of photoresist patterns.

Second barrier patterns 133, second bonding pads 135 and second bufferpatterns 137, which are sequentially stacked, may be formed on thesecond metal patterns 110 b by etching the second barrier layer, thesecond pad layer and the second buffer layer, which are sequentiallystacked, using the mask patterns 140 as an etching mask.

The second barrier patterns 133, the second bonding pads 135 and thesecond buffer patterns 137, which are sequentially stacked, may fill thesecond pad holes 130 a. The second barrier patterns 133, the secondbonding pads 135 and the second buffer patterns 137, which aresequentially stacked, may be formed on (or partially covering) the topsurface of the upper insulating layer 130 around the second pad holes130 a. As such, the second barrier patterns 133, the second bonding pads135 and the second buffer patterns 137, which are sequentially stacked,may be formed passing through the upper insulating layer 130, the lowerinsulating layer 120 and the insulating barrier layer 115. The secondbarrier patterns 133, the second bonding pads 135 and the second bufferpatterns 137 may be electrically connected to the second metal patterns110 b.

The second barrier patterns 133, the second bonding pads 135 and thesecond buffer patterns 137 may have a top surface which is positioned ata higher level than the upper insulating layer 130. The second bondingpads 135 may have a first region which is positioned at the same levelas the first bonding pads 125 and a second region which is positioned ata higher level than the first bonding pads 135. The second region mayhave a greater width than that of the first region.

Referring to FIG. 1E, the mask patterns 140 may be removed. Insulatingspacers 145 may be formed on the side walls of the second barrierpatterns 133, the second bonding pads 135 and the second buffer patterns137, sequentially stacked. The insulating spacers 145 may be formed of amaterial which has an etch selectivity with respect to the upperinsulating layer 130. For example, if forming the upper insulating layer130 with a silicon oxide layer, the insulating spacers 145 may be formedof a silicon nitride layer.

The upper insulating layer 130 may be etched using the insulatingspacers 145 and the second buffer patterns 137 as an etching mask untilthe first buffer patterns 127 is exposed. While etching the upperinsulating layer 130, the top surfaces of the first and second bondingpads 125 and 135 may be protected by the first and second bufferpatterns (127 and 137 in FIG. 1D). The first bonding pads 125 and thesecond bonding pads 135 may be exposed by removing the first bufferpatterns 127 and the second buffer patterns 137.

As shown in FIG. 2, the upper insulating layer 130 may be etched, afterremoving the mask patterns 140, using the second buffer patterns 137 asan etching mask until the first buffer patterns 127 is exposed. A spacerinsulating layer may be formed on the substrate, which has the firstbuffer patterns 127, exposed by etching the upper insulating layer 130.Insulating spacers 245 may be formed by anisotropically etching thespacer insulating layer. The insulating spacers 245 may cover the sidewalls of the second bonding pads 135. The insulating spacers 245 mayextend downward along the side walls.

It can be seen from the top view that a portion of the first bondingpads 135 may be covered with the insulating spacers 245 if the distancebetween the side walls of the second bonding pads 135 and the side wallsof the first bonding pads 135 is equal or less than the thickness of theinsulating spacers 245.

As described above, example embodiments provide a bonding pad structurewhich is capable of decreasing the distance between adjacent bondingpads, an electronic device having the bonding pad structure and a methodof fabricating the electronic device.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although a few example embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible in example embodiments withoutmaterially departing from the novel teachings and advantages of thepresent invention. Accordingly, all such modifications are intended tobe included within the scope of this invention as defined in the claims.In the claims, means-plus-function clauses are intended to cover thestructures described herein as performing the recited function, and notonly structural equivalents but also equivalent structures. Therefore,it is to be understood that the foregoing is illustrative of the presentinvention and is not to be construed as limited to the specificembodiments disclosed, and that modifications to the disclosedembodiments, as well as other embodiments, are intended to be includedwithin the scope of the appended claims. The present invention isdefined by the following claims, with equivalents of the claims to beincluded therein.

1. A bonding pad structure, comprising: a first bonding pad on asubstrate; and a second bonding pad spaced apart from the first bondingpad, wherein the second bonding pad has a top surface at a higher levelthan the first bonding pad.
 2. The bonding pad structure according toclaim 1, wherein the second bonding pad has a first region at a samelevel as the first bonding pad and a second region at a higher levelthan the first bonding pad, the second region having a greater widththan that of the first region.
 3. The bonding pad structure according toclaim 1, wherein the first bonding pad and the second bonding pad havebottom surfaces at a same level.
 4. The bonding pad structure accordingto claim 1, further comprising: an insulating layer interposed betweenthe first bonding pad and the second bonding pad, wherein the insulatinglayer has a top surface at a higher level than the first bonding pad. 5.The bonding pad structure according to claim 4, wherein the secondbonding pad covers a portion of a top surface of the insulating layer.6. The bonding pad structure according to claim 1, further comprising:an insulating spacer on a side wall of the second bonding pad.
 7. Thebonding pad structure according to claim 6, wherein the insulatingspacer covers the side wall of the second bonding pad and a portion ofthe first bonding pad.
 8. An electronic device, comprising: the bondingpad structure according to claim 1 including at least two first bondingpads and at least two second bonding pads; a lower insulating layer onthe substrate, wherein the first bonding pads pass through the lowerinsulating layer; and an upper insulating layer on the lower insulatinglayer around the first bonding pads, wherein the second bonding padssequentially pass through the upper insulating layer and the lowerinsulating layer.
 9. The electronic device according to claim 8, furthercomprising: an interlayer insulating layer interposed between thesubstrate and the lower insulating layer; and metal patterns passingthrough the interlayer insulating layer, wherein the metal patterns areelectrically connected to the first bonding pads and the second bondingpads.
 10. The electronic device according to claim 8, wherein each ofthe first bonding pads covers a portion of a top surface of the lowerinsulating layer.
 11. The electronic device according to claim 8,wherein the upper insulating layer covers a portion of top surfaces ofthe first bonding pads.
 12. The electronic device according to claim 8,wherein the second bonding pads cover a portion of a top surface of theupper insulating layer.
 13. The electronic device according to claim 8,further comprising: insulating spacers on side walls of the secondbonding pads.
 14. The electronic device according to claim 13, whereinthe insulating spacers cover the side walls of the second bonding padsand a portion of the first bonding pads.